DIGITAL DESIGN THROUGH VERILOG

 DIGITAL DESIGN THROUGH VERILOG Essay

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Code Zero: L0422

Arranged No . 1

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

4 B. Technology. II Search engine optimization., I Mid-Term Examinations, Jan/Feb – 2011 DIGITAL DESIGN AND STYLE THROUGH VERILOG

Objective Exam

Name: ______________________________ Hall Solution No .

A

Answer All Questions. All Questions Carry Equal Represents. Time: 20 Min. Represents: 20.

I actually

Choose the accurate alternative:

1 )

Verilog HDL is used to model

A) An Analog System

B) A Digital Program

2 .

a few.

C) A Discrete System

[

]

D)All the above

Which of the following is definitely not an white-colored space personality

A) \t

B) \n

C) \b

D) \s

$stop is employed for

A) break stage

[

D) eliminate the program

B) start stage

C) preliminary point

[

G

L

3rd there�s r

O

]

]

5.

To provide program by which a module may communicate with it is environment what its environment what can be utilized.

[

]

A) segments

B) jacks

C) parameters

D) none

5.

In Verilog, constants defined in a module by the keyword

A) Constant

B) Parameter

C) Const

D) None

Just how many common sense values defined in Verilog with their strength's A) One particular

B) Two

C) Three

D) Four

6.

Watts

U

Big t

N

[

]

[

]

7.

Which from the following represents Reduction operator NOR

A) ^ ~

B) ~

C) ~ ^

D) |~

[

]

8.

In case the input to a tranif1 bidirectional switch is usually supply0, then your output signal strength is [ A) weak0

B) strong0

C) poor 1

D) strong1

]

being unfaithful.

Trireg netting can have got _________ values

A) zero, 1, back button, z

B) 0, you, z just

]

10.

T

[

C) zero, 1, times only

D) 0, you only

It is legal to connect internal and external items of different ________ when making Intermodule port links.

[

]

A) Sizes

B) Variables

C) Constants

D) None

Cont……2

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Code No: L0422

: 2:

Set No . 1

II

Fill out the blanks

11.

In Verilog, with respect to gate delay's, which hold off is the minimum of all delays ___________

doze.

Process of switching a high–level description of design into an improved gate level representation is known as _____________

13.

Delay linked to a gateway output transition to a ‘0' by another benefit is called __________

14.

To represent physical interconnection between structural elements __________data type can be utilised.

15.

Acted continuous job of delay can be used in ____________ modeling.

16.

Continuous blocks in behavioral building are specified with __________, _________Keywords.

17.

Delay connected with a door output transition to a ‘1' from the other value is called _________delay.

18.

__________is utilized to verify design in real-life environment with real program software jogging on system

19.

Postpone associated with a gate output transition towards the high impedance value (Z) from other benefit is called ____________

20.

Event based time control is achievable with _____________modeling

D

D

R

O

W

U

T

In

-oOo-

M

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Code Not any: L0422

Established No . a couple of

JAWAHARLAL NEHRU TECHNOLOGICAL COLLEGE OR UNIVERSITY HYDERABAD

4 B. Technical. II Search engine optimization., I Mid-Term Examinations, Jan/Feb – 2011 DIGITAL DESIGN THROUGH VERILOG

Objective Examination

Name: ______________________________ Hall Solution No .

A

Answer Your concerns. All Questions Bring Equal Markings. Time: twenty Min. Signifies: 20.

My spouse and i

Choose the accurate alternative:

1 )

To provide program by which a module may communicate with its environment what its environment what works extremely well.

[

]

A) quests

B) jacks

C) variables

D) none

2 .

In Verilog, constants defined within a module by keyword

A) Constant

B) Parameter

C) Const

D) None

Just how many logic values described in Verilog with their strength's A) One particular

B) Two

C) 3

D) Several

3.

[

Deb

L

Ur

O

]

[

]

some.

Which in the following signifies Reduction user NOR

A) ^ ~

B) ~

C) ~ ^

D) |~

[

]

5.

In the event the input to a tranif1 bidirectional switch can be...

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